1. Field of the Invention
The present invention relates to data communication systems and more particularly to use of an externally provided reference clock by circuits used in acquisition of a timing signal associated with the data communication
2. Description of the Related Art
Communication systems frequently transmit data in which the clock is embedded in the data stream rather than sent as a separate signal. When the data stream is received, a clock and data recovery circuit recovers the embedded clock and retimes the received data to the recovered clock. Traditionally, a phase-locked loop (PLL) has been used to perform the clock recovery operation. FIG. 1 shows a block diagram of a traditional PLL configured for a clock and data recovery application. The phase-locked loop 100 includes a phase detector 102, which receives the input data signal conveyed on node 104 and also receives the VCO output clock signal conveyed on node 106 from the voltage controlled oscillator (VCO) 108. The phase detector 102 generates an error signal 10, which is a unction of the phase difference between the input data signal and the VCO output clock signal. The phase detector 102 may also include additional circuitry to generate the reconstructed data on output node 114.
In order to help the VCO acquire the frequency of the input data stream, it has been common to use a reference clock to center the VCO output frequency for a nominal output that approximates the frequency of the input data stream. In a typical application, the VCO will multiply the reference clock by a predetermined (or selectable factor), e.g., 16, to achieve the nominal VCO output. For example, if the multiplication factor is 16, for a 2.7 Gbps data rate, the reference clock is 168.75 MHz. The requirement for a reference clock (generally differential) adds both cost and design complexity to the system in which a clock and data recovery circuit resides. The clock has to be supplied by a relatively high cost crystal oscillator component and distributed to the clock and data recovery circuit using design practices appropriate for high speed clock signals.
In addition to using the reference clock to center the nominal output of the PLL, the reference clock is also used to determine whether lock has been achieved. Typical lock-detect circuitry compares the reference clock to a divided down version of the recovered clock, and if the difference between the two clocks is sufficiently high, the PLL is determined to be out-of-lock.
In some cases the frequency of the reference clock may be chosen to be one of several possible frequencies, and the internal VCO operates at the same frequency, irrespective of which one of the reference clock frequencies is provided. In this case the divider which generates the divided-down VCO clock must change its divide value to properly generate a clock having a frequency nominally equal to the external reference clock. In other cases the VCO may always operate at a fixed multiple of the externally provided reference clock. Nonetheless, it may still be desirable to know which of the possible reference clock frequencies is being provided to the device so that, for example, certain characteristics of the phase locked loop may be optimized for the particular frequency of operation.
Traditionally, integrated circuit devices which may be operated with more than one reference clock frequency include one or more additional external input pins to communicate to the device which of the frequencies is being provided to the device. For example, if any of four different reference clock frequencies may be used, two additional input pins are traditionally provided to the device, and a binary code is conveyed on the pair of pins to identify which of the reference clock frequencies is presented to the device.
Unfortunately, integrated circuit pins are a valuable resource for many integrated circuit devices and allocating two of such pins for a reference clock select function may result in fewer pins available for other, more important functionality requirements, or worse, may simply not be available to allocate at all. Even if extra integrated circuit pins are available for a reference clock select function, the board design or other aspects of the system design are, in all likelihood, more complicated.
One particular application area in which the integrated circuit package size is important is fiber optic transmit and receive electronics that recover timing and drive the optics for serial data communication applications. One example of such a circuit includes a clock and data recovery circuit, which may be housed within an optical module housing where space is very critical.
What is desired is an improved technique which allows a communication system to acquire a clock signal embedded in an input data stream without having to use a reference clock signal and which also allows the use of a reference clock signal if desired. It would be further desirable to detect, without requiring the use of dedicated input pins, referenceless mode of operation in which no reference clock is used and reference clock mode of operation and to further detect which of several possible reference clock frequencies are being received if a reference clock is being used.
An integrated circuit determines which of two possible modes of operation, a referenceless or reference clock mode of operation, is used based on a detected frequency of an externally-provided frequency reference signal. The frequency is detected without any additional externally provided signal to indicate the mode of operation or the frequency of the reference clock. If the frequency detection circuit detects a frequency below a predetermined threshold, referenceless mode of operation is indicated. Otherwise, reference clock mode of operation is indicated. In referenceless mode of operation such operations as frequency acquisition and lock detect are performed without the use of a reference clock. In reference clock mode the reference clock is used for such operations as frequency acquisition and lock detect.
In one embodiment an integrated circuit includes an input terminal for receiving an input signal and a frequency detection circuit responsive to a detected frequency of the input signal, to determine according to the detected frequency whether the integrated circuit is operating in a referenceless mode of operation or in a reference clock mode of operation.
Theses and other objects, features, and advantages of the present invention may be more fully appreciated upon review of the detailed description given below.